WFC VIC
#360 ·
frontplane is blue, backplane is red
start by tracing power routing to every chip to verify.
also seems to me that pin 3 of the pll goes to the 10k resistor called point "G", the input of figure 5.
(because pin 4 of PLL- VCO signal out, goes to pin 14 of 4017, pin 14 is the clock input and i would suspect that according to the photo and according to the figure 7 schematic this would be true)
Basically signal goes out on pin 4 and comes back on pin 3 so if you switch in one of the 4017s the frequency is divided and comes back from pin12 carry to pin 3 pll and at this point goes to point "G"
if pll pin 4 went to point "G" the 4017 dividers wouldnt work...
also here is the multisim simulation for figures 3, 4 voltage circuit... still have to test it in the real world but its updated based on the VIC CARD revelations...
to me it looks just like his drawing... thing is his drawing looks like a regular square wave untill youve played with this circuit